Programmable logic devices (PLD) such as field programmable gate arrays (FPGA) and complex programmable logic devices (CPLD), are integrated circuits that can be programmed by users to perform customized logic functions. In a typical design process a user defines customized logic functions using a computer aided design software tool, such as schematic capture or hardware description language (HDL). The software tool then implements the design for a specified programmable logic device type using configurable logic block resources available on that device. The implemented design is stored in a configuration data file. This data file is then loaded into a programmable logic device, configuring the programmable logic device to perform the user's defined customized logic functions.
A programmable logic device is typically mounted on a printed circuit board (PCB) as part of an electronic system. At least one voltage regulator device mounted on the printed circuit board, or external to the printed circuit board, provides power supply to the programmable logic device. The electric circuit comprising the voltage regulator, the interconnects from the voltage regulator to the on-die circuits of the programmable logic device, and any decoupling capacitors is called power distribution network (PDN).
Typical programmable logic device dies are fabricated in complementary metal-oxide-semiconductor (CMOS) process. In digital circuits fabricated in CMOS process when a signal transitions from a logic state “false” to a logic state “true” a transient electric current flows from the positive node of the power supply into the digital circuit. Similarly when a signal transitions from a logic state “true” to a logic state “false” a transient electric current flows from the digital circuit into the negative node of the power supply. These transient currents flow through the power distribution network and generate transient voltage drops on the electrical impedance of the power distribution components through which these transient currents flow. As a direct consequence of the transient voltage drops, the on-die positive voltage supply drops momentarily and the on-die negative voltage supply rises momentarily. The on-die circuits see these momentary supply voltage drops and rises as power supply noise. This noise is called switching noise because the switching of signal logic states in the digital circuit generates it.
In a typical programmable logic device multiple signals may switch at the same moment in time increasing the magnitude of switching noise on the positive and negative supplies. This effect is commonly refereed to as simultaneous switching noise (SSN). Simultaneous switching noise (SSN) degrade the performance of the programmable logic device circuits. The magnitude of the simultaneous switching noise (SSN) depends on the number of switching gates of the programmable logic device, the switching speed, and the electrical impedance of the power distribution network (PDN).
In general, the power distribution network impedance is a complex quantity having the magnitude dependent on frequency. As a direct consequence, the magnitude of simultaneous switching noise depends on the frequency of operation of the programmable logic device. Most power distribution networks present impedance magnitude peaks at some frequencies, called resonance peaks. If operating frequency of the programmable logic device, or harmonics of the operating frequency, overlap with a resonance peak of the power distribution network, then significant noise is generated on the on-die voltage supplies.
Knowing the frequency characteristics of the power distribution impedance can help reduce the simultaneously switching noise by configuring the programmable logic device to operate at frequencies that do not overlap with the resonance peak frequencies. Alternately, designers can modify the power distribution network circuit so that the resonance peaks do not overlap with operating frequencies or their harmonics, which is typically done through adjusting the values of decoupling capacitors.
It is therefore desirable to know the frequency characteristic of the power distribution impedance. Most of the existing techniques measure only the section of the power distribution impedance of the printed circuit board, and do not address the sections in the interface to the package, in the package, in the interface to the die, and in the die. While measurements of the printed circuit board can be very accurate, many times the resonance peak frequencies change when the package with die is attached to the board. Therefore, on-die measurement techniques can provide more accurate results. Typical on-die measurement techniques use built-in dedicated circuits that measure the power distribution network impedance. These built-in measurement circuits have to be implemented during the fabrication of integrated circuits, and most of the programmable logic devices (PLD) available on the market do not have such built-in measurement capabilities.
It would therefore be desirable to be able to measure on-die the electrical impedance of the power distribution network of a programmable logic device (PLD) by using only general configurable logic blocks available in any programmable logic device (PLD), without the need of built-in dedicated circuits.